Cornell imaging method reveals atomic scale defects in semiconductor chips
A Cornell led team has directly imaged atomic scale defects inside advanced computer chips, using a high resolution three dimensional electron microscopy technique developed with Taiwan Semiconductor Manufacturing Company and Advanced Semiconductor Materials. The method, based on multislice electron ptychography and an electron microscope pixel array detector, reveals irregular interface features in transistor channels that first author Shake Karapetyan describes as “mouse bite” defects, which can undermine chip performance at the few nanometer scale.
As transistor channels in state of the art devices now measure only about 15 to 18 atoms across, each atom’s position has a direct impact on how well current flows. The Cornell group used its high dynamic range detector, which holds a Guinness World Record for resolution, to record detailed electron scattering patterns as the beam passed through prototype gate all around transistors. By computationally reconstructing these patterns with multislice electron ptychography, the researchers produced three dimensional images with sub angstrom lateral resolution and nanometer depth resolution, allowing them to measure interface roughness, strain and buried defects in the wrapped gate oxide and silicon channel.
Project leader David Muller said there is currently no other way to view such defects at true atomic resolution, making the technique a powerful new tool for debugging chips during development. He compared earlier generations of electron microscopes to biplanes and the present instrument to a jet aircraft, reflecting the leap in capability achieved by combining advanced detectors with modern reconstruction algorithms. The work builds on Muller’s long standing collaboration with ASM executive Glen Wilk, with whom he helped introduce hafnium oxide gate dielectrics at Bell Labs in the late 1990s, a technology that soon became standard across the industry.
In the new study, the team applied the Cornell developed detector to modern gate all around structures grown at leading nanoelectronics facilities, including imec, to test how well the method could resolve buried features. After reconstructing the full three dimensional dataset and tracking individual atomic columns, they identified distinct roughness profiles at the top and bottom interfaces of the transistor channels, which reflect the different processing conditions used during fabrication. The measurements show that only around sixty percent of atoms in the thin silicon channel remain in a bulk like environment, as the material gradually relaxes away from the rough interfaces.
The authors argue that such quantitative data on interface roughness and strain, extracted from a single measurement, provide key input parameters for modeling charge transport and reliability in next generation devices. Given that advanced chips can require hundreds or even thousands of individual processing steps, the ability to inspect the atomic structure after each major stage could help engineers tune temperatures, etch conditions and deposition processes far more precisely than before. The researchers expect the technique to find applications across technologies that rely on extreme nanoscale control, from smartphones and laptops to automotive electronics, artificial intelligence data centers and quantum computing hardware.
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